The present invention relates to a semiconductor integrated circuit device for driving a liquid crystal of a liquid crystal display panel, for a thermal head used for a printer of a facsimile, for driving a step motor of a quartz clock, and for a nonvolatile memory, and to a manufacturing method therefor.
The present invention relates to an electronic circuit using the above semiconductor integrated circuit, and to a manufacturing method therefor.
The present invention relates to an insulating gate field effect type semiconductor integrated circuit having a high withstand voltage construction, more specifically to a driver integrated circuit for driving a liquid crystal, for driving a thermo-sensitive register, and the like.
The present invention relates to a semiconductor device, more specifically to a semiconductor device having a plurality of driving transistors such as a semiconductor integrated circuit for a thermal head, and having output pads for the driving transistors, respectively.
The present invention relates to a semiconductor circuit device having an external electrically connecting terminal on an electronic circuit.
The present invention relates to a stable operation of a semiconductor integrated circuit device.
The present invention specifically relates to a semiconductor integrated circuit device having bump electrodes on an electronic circuit,
The present invention relates to a semiconductor integrated circuit device having a built-in protecting circuit for protecting internal elements.
The present invention relates to a semiconductor integrated circuit device having bump electrodes.
More specifically, the present invention relates to semiconductor integrated circuit, such as a semiconductor integrated circuit for driving a thermal head, in which the side of a chip is remarkably long as compared with the area of the chip.
The present invention relates to a method of manufacturing a semiconductor integrated circuit, more specifically to a method of manufacturing a semiconductor integrated circuit, such as a semiconductor integrated circuit for driving a thermal head, which is remarkably elongated, and having a long periphery length.
The present invention relates to a semiconductor integrated circuit in which a plurality of transistors are integrated on the same substrate, particularly to a semiconductor integrated circuit in which a pad portion as an external connecting terminal is disposed on a transistor.
The present invention relates to an electronic circuit and a manufacturing method therefor, particularly to an electronic circuit including an integrated circuit which is implemented on a printed circuit board in a face down manner, more specifically to an electronic circuit used for an electronic clock.
The conventional semiconductor device (semiconductor integrated circuit) for a thermal head has a switching function for applying an electric current of about 10 mA through a plurality of resistors of several k.OMEGA. arranged in line along a thermal-sensitive paper corresponding to a printing information. The respective thermal-sensitive resistors are electrically connected to an external connecting terminal disposed on a surface of the semiconductor device.
FIG. 2 is a sectional view of an output portion of a general semiconductor device for a thermal head. Thermal-sensitive resistors and semiconductor devices are disposed away from each other in two dimensions on a thermal head substrate. The thermal-sensitive resistors are directly connected to bonded wires 11. The bonded wire 11 is mechanically and electrically connected to a pad region made of an aluminum interconnection by a bonding process. The pad region is comprised of an aluminum film pattern formed, used for connection to the external circuit, by perforating a final passivation film 10 on an aluminum interconnection 9. Below the pad region are disposed an intermediate insulating film 8 and a field insulating film 6 which bear mechanical stress at the bonding process. The aluminum interconnection 9 of the pad region is electrically connected to a drain region of a resistor driving insulating gate field effect transistor arranged in two dimensions through a contact region 12. The drain region, being of a high withstand voltage construction, is comprised of a first drain region 3B comprising a low density impurity region, and a second drain region 3A comprising a high density impurity region. A high voltage of about 30 V is added to the thermal-sensitive resistors in order to apply a large electric current of about 10 mA thereto. Accordingly, when the transistor which functions as a switch is turned off, a high voltage of about 30 V is added to the drain region. A plurality of the transistors for switching the respective thermal-sensitive resistors are arranged along a longitudinal direction of the semiconductor by the number of the resistors in a row as shown in FIG. 3.
An example of the conventional semiconductor device is shown in FIG. 3. FIG. 3 is a plane view of a semiconductor integrated circuit for a thermal head. Output pads 01, 02, . . . , ON and electric source pads P1, P2 and the like are arranged on a periphery of a chip 50. The circuit on which transistors are integrated is arranged away from an external leading electrode in two dimensions. In other words, driving transistors T1, T2, . . . , TN are arranged so as to be electrically connected to the corresponding output pads, and further logic circuits L1, L2, . . . , LN for controlling the respective driving transistors are arranged cycle-periodically along a longitudinal direction of the chip 50. The external leading electrode is comprised of a perforation 92 disposed on the final protecting film and a bump 93 is disposed on the perforation 92. The bump in FIG. 3 may be replaced by a bonding.
FIG. 4 shows a conventional semiconductor integrated circuit device. A plurality of pad electrodes 603 as terminals which are to be connected to the external circuit are disposed on a semiconductor substrate 601. The pad electrodes 603 are connected to an internal electronic circuit 602 through protecting circuits 604, respectively. The protecting circuit 604 aims to discharge an eddy-current in order to prevent the breakdown of the internal electronic circuit 602 due to the eddy-current caused by static electricity and noise inputted to the internal electronic circuit 602 from the external circuit. Basically, one protecting circuit 604 is required for one pad electrode 603. Also, in order to discharge the eddy-current, the protecting circuit 604 is required to be sufficiently away from the internal circuit 602 in such a manner that the discharging electric charge does not reach the internal circuit 602.
However, the conventional semiconductor device for the thermal head has the problems described below. That is, as shown in FIG. 2, the transistors and the bonding pads are required to be disposed away from each other in two dimensions, so that the area of the semiconductor device becomes large, which makes it difficult to lower the manufacturing cost.
Also, the conventional high withstand voltage MOS transistor has a shallow diffusion depth of a low density drain region used for obtaining the high withstand voltage characteristic, which requires the transistor having a large area in order for a large electric current to flow therethrough against the increase of the resistance thereat. Further, when raising the density of the low density drain region for obtaining the high withstand voltage characteristic in order to reduce the resistance thereof, the withstand voltage of the drain region is excessively reduced down to not greater than 10 V. Otherwise, when the diffusion depth is made deeper while remaining the low density, the low density drain region for obtaining the high withstand voltage characteristic excessively becomes large in a lateral direction also, which makes the transistor excessively large.
The conventional semiconductor device shown in FIG. 2 has an disadvantage that, since the active element region on which the transistors are arranged and the external leading electrode are located separately on the individual locations, the area of the chip is large, thereby preventing the reduction in the cost of the chip.
The conventional semiconductor device has a problem that, since the external electrically connecting terminal-use metal electrode is formed larger than the size of the opening portion of the passivation film, on the region in which the external electrically connecting terminal-use metal electrode exists cannot be formed thereover the interconnection of the same metal, thereby preventing the reduction in the chip size.
In the technique of directly implementing a semiconductor integrated circuit on a glass substrate such as COG (Chip on Glass), the semiconductor integrated circuit used for a liquid crystal and the like is exposed to the light entering through the glass of the liquid crystal panel, thereby failing to function properly. As a result, the light shielding is required, and therefore the metal interconnections in the integrated circuit are used as the light shielding film In a case where the metal interconnections are used in the semiconductor integrated circuit used for the liquid crystal panel, there are caused gaps between the interconnections and the light shielding film region, which makes it impossible to shield the light effectively, since the interconnections are essentially used for the connection between the elements. Also, there are easily caused a case that the voltage of the light shielding film cannot be stabilized, since the light is shielded at a location between the interconnections. In this case, there is unexpectedly caused a floating state, which is not preferable in view of the stable operation.
In the conventional semiconductor device, a pressure is applied to a portion between the external circuit and the semiconductor substrate in order to connect the bump electrode with the external circuit. On this occasion, if the passivation film and the polysilicon resistor are formed below the bump electrode, the passivation film and the polysilicon resistor also are applied with a force, thereby causing cracks on the passivation film to lower the reliability of the semiconductor integrated circuit, and deforming the polysilicon resistor to change the resistance value and therefore lowering the characteristic of the semiconductor integrated circuit.
In the conventional semiconductor device, a pressure is applied to a portion between the bonded wire and the semiconductor substrate in order to connect the external electrically connecting terminal-use aluminum electrode with the bonded wire. On this occasion, if the passivation film and the polysilicon resistor are formed below the bump electrode, the passivation film and the polysilicon resistor also are applied with a force, thereby causing cracks on the passivation film to lower the reliability of the semiconductor integrated circuit, and deforming the polysilicon resistor to change the resistance value and therefore lowering the characteristic of the semiconductor integrated circuit.
The conventional semiconductor device requires the protecting circuits 604 which is identical in number with the pad electrodes 603 as shown in FIG. 4. Then, the protecting circuits 604 are required to be located away from the internal electronic circuits 602, thereby enlarging the area of the protecting circuits 604 which occupy the semiconductor substrate 601 to increase the size of the chip of the semiconductor integrated circuit device, which excessively increases of the cost of the semiconductor integrated circuit device.
The conventional semiconductor integrated circuit, having a dummy bump region, therefore has an drawback to increase the chip size and then increases the cost of the chip.
In the corner portion of the conventional semiconductor integrated circuit device, the silicone substrate on the chip is, before implementation, cut to be shaped like a rectangular. The diffusion region constituting the semiconductor integrated circuit is disposed inside the chip about 40 .mu.m away from the scribed surface.
However, the conventional semiconductor integrated circuit device has a drawback that, since the diffusion region is designed/manufactured to be located not less than 40 .mu.m away from the scribed surface, the chip size is large and therefore the cost of the chip cannot be reduced.
It is found cut that the conventional semiconductor integrated circuit device has a drawback to excessively change the characteristic of the integrated circuit due to the static electricity when the pad portion is disposed on the separation region. In other words, when a high voltage is applied to the pad portion as the external connecting terminal, a small amount of electric current unexpectedly flows between electrically separated different N+impurity regions formed in a construction of sandwiching the separation region therebetween, although the detail mechanism is still unclear.
It is known from our experiments that the small amount of electric current is recovered by applying ultraviolet irradiation and high temperature to the semiconductor device. However, there is a problem that it is practically impossible to execute the ultraviolet irradiation on all such occasions.
The conventional integrated circuit using the wire bonding has a problem that the chip size cannot be reduced since the active element region and the pad portion are located on separate regions. Further, there is a problem that, since the pad and the printed circuit board are electrically connected through the bonded wire and the lead, the printed circuit board on which the chips are implemented cannot be sized down. Besides, there are problems that the pad and the printed circuit board are connected by a connection method including three-times connection manner, which cannot be carried out simultaneously, thereby be capable of reducing the manufacturing time. Accordingly, as apparent from the above, the chip and the implemented device cannot be sized down and further the manufacturing processes are long and complicated, whereby the implemented electronic circuit cannot be manufactured at a low cost.
It is, therefore, an object of the present invention to reduce the area of the transistor and the pad and therefore to reduce the manufacturing cost of the device, in order to solve the above-mentioned conventional problems.
Further, it is an object of the present invention to obtain a semiconductor device which is capable of applying a large electric current even with the small area in a high withstand voltage MOS transistor in which a high voltage of not less than 10 V is applied to a drain region.
Still further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor device which is capable of reducing the cost of the device due to the reduction of the chip size.
Also, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which is capable of reducing the size of the chip, on which an external electrically connecting terminal-use metal electrode is formed on an electronic circuit even with the small area without changing the characteristic of the circuit.
Further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor device which, being superior in reliability, has a bump electrode at an electronic circuit without changing the characteristic of the circuit.
Still further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which, being superior in reliability, has an external electrically connecting terminal-use aluminum electrode at an electronic circuit without changing the characteristic of the circuit.
Moreover, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which, being superior in reliability, has an external electrically connecting terminal-use metal electrode at an electronic circuit without changing the characteristic of the circuit.
Further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which prevents the enlargement of the area of the protecting circuit.
Still further, it is an object of the present invention to solve she above drawbacks then providing a semiconductor integrated circuit device which is capable of reducing the cost of the device due to the reduction of the chip size.
Moreover, it is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device which is capable of reducing the cost of the device due to the reduction of the chip size, more specifically to provide a method of manufacturing a semiconductor integrated circuit device which is capable of reducing the area of the chip of an integrated circuit for a thermal head, or a minute integrated circuit such as a closely contact type line sensor integrated circuit.
Besides, it is an object of the present invention to provide a semiconductor device which prevents the increase of the leak electric current even if the static electricity, which is optionally applied to the pad electrode at the time of the implementation, is applied, in the semiconductor device in which the pad portion is laminated on the transistors in order to reduce the area of the semiconductor integrated circuit.
In is an object of the present invention to solve the above problems then reducing the chip size, sizing down the implemented electronic circuit, improving the manufacturing efficiency of the electronic circuit, and reducing the cost of the device